1. Field of the Invention
The present invention relates a lithographic apparatus and device manufacturing method.
2. Related Art
A lithographic apparatus is a machine that applies a desired pattern onto a substrate or part of a substrate. A lithographic apparatus can be used, for example, in the manufacture of flat panel displays, integrated circuits (ICs) and other devices involving fine structures. In a conventional apparatus, a patterning device, which can be referred to as a mask or a reticle, can be used to generate a circuit pattern corresponding to an individual layer of a flat panel display (or other device). This pattern can be transferred onto all or part of the substrate (e.g., a glass plate), by imaging onto a layer of radiation-sensitive material (e.g., resist) provided on the substrate.
Instead of a circuit pattern, the patterning device can be used to generate other patterns, for example a color filter pattern or a matrix of dots. Instead of a mask, the patterning device can be a patterning array that comprises an array of individually controllable elements. The pattern can be changed more quickly and for less cost in such a system compared to a mask-based system.
A flat panel display substrate is typically rectangular in shape. Lithographic apparatus designed to expose a substrate of this type can provide an exposure region that covers a full width of the rectangular substrate, or covers a portion of the width (for example half of the width). The substrate can be scanned underneath the exposure region, while the mask or reticle is synchronously scanned through a beam. In this way, the pattern is transferred to the substrate. If the exposure region covers the full width of the substrate then exposure can be completed with a single scan. If the exposure region covers, for example, half of the width of the substrate, then the substrate can be moved transversely after the first scan, and a further scan is typically performed to expose the remainder of the substrate.
It is desired to have patterning devices with large numbers of individually controllable elements, e.g., in the 10 million range, in order to provide smaller and smaller features with higher resolutions. However, information handling capability of existing patterning device transistors is too low because of a large required energy (e.g., amount of information) per individually controllable device (bit), e.g., approximately 500 nJ/bit. A total system power required to drive the patterning device is too large because of the high input voltage (e.g., greater than about 20 V). At this power, the heat generated in the device from processing the information required to control a large amount of the individually controllable elements could damage or destroy the device. Also, a single-ended signal path architecture of the current devices introduces a serious limit to the resolution and linearity of movement of the individually controllable devices (e.g., limited to 8 bits), where at least 10 bits are desired. The two-quadrant architecture of the current devices introduces serious limits to timing margins, offset, and gain adjustments. Fabrication of the current devices requires high-voltage IC technology, which is not compatible with high-speed IC technology. The large mirror sizes (e.g., 16×16 μm) of the current devices limits the number of pixels per chip to about 2,000,000. The use of aluminum mirrors requires special operation conditions to reduce the influence of mechanical memory effects (e.g., hysteresis) and limits the mechanical life-time and the pattern data update rate of the device (e.g., a maximum update rate of about 2 kHz). Furthermore, most of the current devices have no on-chip electronics for automated self-test, temperature measurement, and special addressing modes for clustered mirrors.
Therefore, what is needed is a more effective and efficient patterning device architecture and control arrangement.